For almost four decades, the progress of microelectronics, as defined by Moore's Law, has been based on the constant optimization of cost-efficient materials, processes and technologies. For sub-100 nm technologies, conventional scaling has become challenging.
Scaling without a loss of performance requires scaling down source/drain regions and gate oxide thickness to maintain sufficient gate control. However, in practice, the pace of scaling both gate oxide and source/drain junctions has reduced. Gate oxide scaling has slowed down due to increased gate leakage, while source/drain junction scaling has been hampered due to increased resistance due to inability to increase dopant solubility. As a practical matter, this manifests as an increase in short channel effects such as drain induced barrier lowering. The loss of gate control and the increase in DIBL result in increased leakage currents in sub-100 nm MOS transistors.
The sub-threshold leakage can be suppressed with increased channel doping, but only with a significant penalty in on-current because of the substantial decrease in mobility due to the high doping levels required to isolate the source from the drain regions. Local strain silicon technologies were introduced to offset the performance loss. In such technologies, the channel or specifically, the inversion region, was strained so as to boost the mobility of the device during operation. This helped to offset the loss arising from the loss in mobility due to, for example, increased Coloumb scattering at high doping levels, which was needed to maintain leakage currents. Nevertheless, strain technologies do not scale with further shrinking geometries and importantly, electron mobilities saturate with strain.
A direct means to increase gate control without increasing gate tunneling leakage currents is to increase the gate dielectric permittivity. Thus, high-k dielectrics have also been introduced to improve gate control. However, even these may not be sufficient to ensure gate control beyond sub-30 nm technologies.
A direct consequence of the poor gate control is the high sub-threshold slope of these extremely scaled devices. A typical transistor requires at least a 10,000× difference between the off-current when the transistor is not activated and the on-current. Devices with high sub-threshold slope require much higher change in gate voltage to produce a required (˜10,000) change in current through the transistor. Low power devices have more stringent requirements between the on- and off-current ratios. For example, a ratio of 107 is desirable for low power devices with low leakage currents. Devices with sub-threshold slopes cannot satisfy these requirements for low power devices. For these devices, simply increasing the threshold voltage to improve (decrease) the off-current will result in very poor on-currents degrading the drive performance of the transistor. Hence, what are needed are devices with low sub-threshold slope that provide good on-current performance.